1. Field of the Invention
The present invention relates to a semiconductor device having a metal layer on a via-hole formed in a semiconductor substrate, such as a microelectromechanical system (MEMS) substrate, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, semiconductor devices having an electroconductive layer on a via-hole formed in a semiconductor substrate, such as a microelectromechanical system (MEMS) substrate, have been used as semiconductor chips for semiconductor memories, image pickup elements, sensors, and light-emitting elements. The via-hole has an electrode pad layer on the bottom thereof. Such semiconductor devices are being applied and developed in various fields, such as the fields of semiconductor packages each including layers of semiconductor chips, the fields of integrated circuit boards for use in micromachines, and the fields of semiconductor modules to be connected to the main bodies of ink jet heads.
Such semiconductor devices include a via-hole, which has an electrode pad layer on the bottom thereof, in a semiconductor substrate. The via-hole has an insulating layer on its sidewall and a metal layer therein (see U.S. Pat. No. 7,442,642). This structure can minimize an electric leakage between the semiconductor substrate and the metal layer in electrically connecting an electrode on the front side to an electrode on the back side of the semiconductor substrate. An interlayer insulating layer is disposed between the semiconductor substrate and the electrode pad layer.
In general, the sidewall of a via-hole in a semiconductor substrate extending from the open end to the bottom thereof is perpendicular to the surfaces of the semiconductor substrate. Thus, there is a problem that the insulating layer or the metal layer tends to be detached from the via-hole in the semiconductor substrate.
In order to solve this problem, in one proposed structure, the opening size of a portion (enlarged portion) close to the bottom of the via-hole (the electrode pad layer) is larger than the opening size of a portion close to the open end of the via-hole (see U.S. Pat. No. 7,732,925). The formation of the insulating layer and the metal layer in the enlarged portion of the via-hole can decrease the likelihood that the insulating layer or the metal layer peels off from the semiconductor substrate because the insulating layer and the metal layer are caught on the enlarged portion. Thus, the insulating layer and the metal layer satisfactorily formed in the enlarged portion can decrease the likelihood that the insulating layer or the metal layer peels off from the semiconductor substrate.
In such a structure having an enlarged portion in a via-hole, however, particles to be deposited sometimes cannot reach the enlarged portion, resulting in a poor insulating layer or metal layer in the enlarged portion. This is particularly noticeable when the insulating layer or the metal layer is formed by physical vapor deposition (hereinafter referred to as PVD). More specifically, in PVD, particles to be deposited linearly enter the via-hole. Thus, the sidewall adjacent to the enlarged portion extending toward the open end blocks the particles from reaching the enlarged portion. This results in insufficient deposition. The insufficient deposition may cause the insulating layer or the metal layer to peel off. A discontinuous metal layer in the enlarged portion may cause disconnection.